Multi-function resistance change memory cells and apparatuses including the same

ABSTRACT

Various embodiments comprise apparatuses having a number of memory cells including drive circuitry to provide signal pulses of a selected time duration and/or amplitude, and an array of resistance change memory cells electrically coupled to the drive circuitry. The resistance change memory cells may be programmed for a range of retention time periods and operating speeds based on the received signal pulse. Additional apparatuses and methods are described.

PRIORITY APPLICATION

This application is a continuation of U.S. application Ser. No.15/237,248, filed Aug. 15, 2016, which is a continuation of U.S.application Ser. No. 14/456,510, filed Aug. 11, 2014, now issued as U.S.Pat. No. 9,418,734, which is a continuation of U.S. application Ser. No.13/428,944, filed Mar. 23, 2012, now issued as U.S. Pat. No. 8,804,399,all of which are incorporated herein by reference in their entirety.

BACKGROUND

Computers and other electronic systems, for example, digitaltelevisions, digital cameras, and cellular phones, often have one ormore memory devices to store information. Increasingly, memory devicesare being reduced in size to achieve a higher density of storagecapacity. However, memory devices also need to meet lower powerrequirements while maintaining high speed access.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a memory device having a memory arraywith memory cells, according to an embodiment:

FIG. 2 shows a partial block diagram of a memory device having a memoryarray including memory cells with access components and memory elements,according to an embodiment;

FIG. 3 shows a schematic diagram of a memory cell having an accesscomponent coupled to a memory element, according to various embodiments;

FIG. 4 is a simplified schematic block diagram of one of severalresistance change memory cell (RCM) memory elements that may be usedwith the memory devices of FIGS. 1 and 2, or may comprise the memorycell of FIG. 3;

FIGS. 5A through 5C show a schematic representation of ionic migrationand localized conductive region formation and growth of a RCM;

FIG. 6 is a voltage-time graph showing a number of programming/erasepulses:

FIG. 7 shows an embodiment of a memory array circuit that may be used toimplement variable resistance states and memory function types;

FIG. 8 is a flowchart showing an embodiment of a method to implementvariable resistance states and memory functions; and

FIG. 9 shows a block diagram of a system embodiment, including a memorydevice.

DETAILED DESCRIPTION

The description that follows includes illustrative apparatuses(circuitry, devices, structures, systems, and the like) and methods(e.g., processes, protocols, sequences, techniques, and technologies)that embody the inventive subject matter. In the following description,for purposes of explanation, numerous specific details are set forth inorder to provide an understanding of various embodiments of theinventive subject matter. It will be evident, however, to those skilledin the art that various embodiments of the inventive subject matter maybe practiced without these specific details. Further, well-knownapparatuses and methods have not been shown in detail so as not toobscure the description of various embodiments.

As used herein, the term “or” may be construed in an inclusive orexclusive sense. Additionally, although various exemplary embodimentsdiscussed below may primarily focus on two-state (e.g., SLC) memorydevices, the embodiments are merely given for clarity of disclosure, andthus, are not limited to apparatuses in the form of SLC memory devicesor even to memory devices in general. As an introduction to the subject,a few embodiments will be described briefly and generally in thefollowing paragraphs, and then a more detailed description, withreference to the figures, will ensue.

Emerging memory technologies may be utilized based on the intrinsiccharacteristics of an advanced memory device, rather than to attempt toforce the device to behave, for example, as a flash memory or randomaccess memory. In various embodiments described herein, managing thememory operations of an advanced memory device from an abstractedinterface entails novel operation schemes.

Various embodiments enable a managed memory solution that capitalizes onthe characteristics of an advanced memory device. For example, aresistance change memory cell (RCM) memory device (e.g., includingdevices such as a programmable metallization cell) exhibits dataretention characteristics that depend on the amplitude and time durationof a signal pulse (e.g., a voltage or current signal). As will becomeapparent, differentiated memory function types may be managed on asingle chip. In some embodiments, all electrical routing is within asingle chip, so that through-silicon vias (TSVs) and critical alignmentbetween adjacent chips are no longer required. In addition, latency maybe reduced on a single chip implementation, as compared with fabricatinga system over multiple chips.

In various embodiments, an apparatus is provided that includes a numberof resistance change memory (RCM) cells. The apparatus includes a firstregion of the RCM cells, a second region of the RCM cells, and drivecircuitry to selectively provide one of a plurality of signal pulsetypes to the first region of the RCM cells and to selectively provide adifferent one of the plurality of signal pulse types to the secondregion of the RCM cells. Each of the plurality of signal pulse typeshave a different attribute and corresponding to a different memoryfunction type

In at least some of embodiments of the apparatus, the attributecomprises an integration of a pulse amplitude and a pulse time duration.

In various embodiments, an apparatus is provided that includes a numberof memory regions; each of the memory regions having a respective numberof resistance change memory cells. A control and select circuitry is todetermine a memory function type to emulate for information to be storedin the apparatus. The control and select circuitry further to select oneof the memory regions in which to store the information. Drive circuitryis to provide to the selected one of the memory regions a pulseconfigured to emulate the determined memory function type for theinformation.

In some embodiments of the apparatus, the memory regions, the controland select circuitry, and the drive circuitry are all formed on a singledie. In some embodiments of the apparatus, the drive circuitry is toprovide a pulse having an amplitude and time duration configured toemulate the determined memory function type. In some embodiments of theapparatus, each of the first and second drive circuits is configured tomatch a respective power requirement of the first memory region and thesecond memory region, respectively.

In various embodiments, a method is provided that includes determiningone of a plurality of memory function types to emulate, and applying aprogramming pulse, having an attribute configured to emulate thedetermined memory function type, to a selected one of the RCM cells.

In various embodiments, an apparatus is provided that includes aresistance change memory (RCM) cell and drive circuitry electricallycoupled to the RCM cell to provide a signal pulse. The signal pulse isconfigurable in both amplitude and time duration to vary a dataretention time of the RCM cell.

In some embodiments of the apparatus, the signal pulse is configurableto vary a localized conduction region formed within the RCM cell toemulate a selected one of a plurality of memory function types. In someembodiments of the apparatus, the drive circuitry is configured to varythe time duration of the signal pulse to vary the data retention time ofthe RCM cell. In some embodiments of the apparatus, the drive circuitryis configured to vary the amplitude of the signal pulse to vary the dataretention time of the RCM cell. In some embodiments of the apparatus,the drive circuitry is configured to provide a sequence of pulses tovary the data retention time of the RCM cell.

In various embodiments, a method of operating a memory device isprovided. The method includes selecting one of a plurality of memoryfunction types to emulate within the memory device, selecting an energylevel per memory cell to be provided in a signal pulse to emulate theselected memory function type, and applying the signal pulse to a memorycell of the memory device

In some embodiments of the method, the selected energy level correspondsto a state of a localized conduction region within the memory cell. Insome embodiments of the method, selecting the energy level per memorycell comprises selecting a time duration of the signal pulse. In someembodiments of the method, selecting the energy level per memory cellcomprises selecting an amplitude of the signal pulse. In someembodiments of the method, selecting the energy level comprisesselecting a current delivered to the memory cell over a duration of thesignal pulse. In some embodiments of the method, selecting the energylevel comprises selecting a current compliance.

In various embodiments, a method of operating a memory device isprovided. The method includes determining a retention period needed forinformation to be stored in the RMC cell and varying an amount of powerconsumed to program the RCM cell depending upon the determined retentionperiod.

In various embodiments, a method of operating a memory device isprovided. The method includes determining a endurance level needed forinformation to be stored in the RMC cell and varying an amount of powerconsumed to program the RCM cell depending upon the determined endurancelevel.

In various embodiments, a method of operating a memory device isprovided. The method includes determining an operating speed needed forinformation to be stored in the RMC cell and varying an amount of powerconsumed to program the RCM cell depending upon the determined operatingspeed.

In various embodiments, a memory device is provided that includes afirst group of RMC cells emulating a first memory type function and asecond group of RMC cells emulating a second memory type function. Thefirst group of RMC cells and the second group of RMC cells are formed ona single integrated circuit

Referring now to FIG. 1, a block diagram of an apparatus in the form ofa memory device 101 is shown. The memory device 101 includes one or morememory arrays 102 having a number (e.g., one or more) of memory cells100 according to an embodiment. The memory cells 100 can be arranged inrows and columns along with access lines 104 (e.g., wordlines to conductsignals WL0 through WLm) and first data lines 106 (e.g., bit lines toconduct signals BL0 through BLn). The memory device 101 can use theaccess lines 104 and the first data lines 106 to transfer information toand from the memory cells 100. A row decoder 107 and a column decoder108 decode address signals A0 through AX on address lines 109 todetermine which ones of the memory cells 100 are to be accessed.

Sense circuitry, such as a sense amplifier circuit 110, operates todetermine the values of information read from the memory cells 100 inthe form of signals on the first data lines 106. The sense amplifiercircuit 110 can also use the signals on the first data lines 106 todetermine the values of information to be written to the memory cells100.

The memory device 101 is further shown to include circuitry 112 totransfer values of information between the memory array 102 andinput/output (I/O) lines 105. Signals DQ0 through DQN on the I/O lines105 can represent values of information read from or to be written intothe memory cells 100. The I/O lines 105 can include nodes of the memorydevice 101 (e.g., pins, solder balls, or other interconnect technologiessuch as controlled collapse chip connection (C4), or flip chip attach(FCA)) on a package where the memory device 101 resides. Other devicesexternal to the memory device 101 (e.g., a memory controller or aprocessor, not shown in FIG. 1) can communicate with the memory device101 through the I/O lines 105, the address lines 109, or the controllines 120.

The memory device 101 can perform memory operations, such as a readoperation, to read values of information from selected ones of thememory cells 100 and a programming operation (also referred to as awrite operation) to program (e.g., to write) information into selectedones of the memory cells 100. The memory device 101 can also perform amemory erase operation to clear information from some or all of thememory cells 100.

A memory control unit 118 controls memory operations using signals onthe control lines 120. Examples of the signals on the control lines 120can include one or more clock signals and other signals to indicatewhich operation (e.g., a programming or read operation) the memorydevice 101 can or should perform. Other devices external to the memorydevice 101 (e.g., a processor or a memory controller) can control thevalues of the control signals on the control lines 120. Specificcombinations of values of the signals on the control lines 120 canproduce a command (e.g., a programming, read, or erase command) that cancause the memory device 101 to perform a corresponding memory operation(e.g., a program, read, or erase operation).

Although various embodiments discussed herein use examples relating to asingle-bit memory storage concept for ease in understanding, theinventive subject matter can be applied to numerous multiple-bit schemesas well. For example, each of the memory cells 100 can be programmed toa different one of at least two data states to represent, for example, avalue of a fractional bit, the value of a single bit or the value ofmultiple bits such as two, three, four, or a higher number of bits.

For example, each of the memory cells 100 can be programmed to one oftwo data states to represent a binary value of “0” or “1” in a singlebit. Such a cell is sometimes called a single-level cell (SLC).

In another example, each of the memory cells 100 can be programmed toone of more than two data states to represent a value of, for example,multiple bits, such as one of four possible values “00,” “01,” “10,” and“11” for two bits, one of eight possible values “000,” “001,” “010,”“011,” “100,” “101,” “110,” and “111” for three bits, or one of anotherset of values for larger numbers of multiple bits. A cell that can beprogrammed to one of more than two data states is sometimes referred toas a multi-level cell (MLC). Various operations on these types of cellsare discussed in more detail, below.

The memory device 101 can receive a supply voltage, including supplyvoltage signals V_(cc) and V_(ss), on a first supply line 130 and asecond supply line 132, respectively. Supply voltage signal V_(ss) can,for example, be at a ground potential (e.g., having a value ofapproximately zero volts). Supply voltage signal V_(cc) can include anexternal voltage supplied to the memory device 101 from an externalpower source such as a battery or alternating-current to direct-current(AC-DC) converter circuitry (not shown in FIG. 1).

The circuitry 112 of the memory device 101 is further shown to include aselect circuit 115 and an input/output (I/O) circuit 116. The selectcircuit 115 can respond to signals SEL1 through SELn to select signalson the first data lines 106 and the second data lines 113 that canrepresent the values of information to be read from or to be programmedinto the memory cells 100. The column decoder 108 can selectivelyactivate the SEL1 through SELn signals based on the A0 through AXaddress signals on the address lines 109. The select circuit 115 canselect the signals on the first data lines 106 and the second data lines113 to provide communication between the memory array 102 and the I/Ocircuit 116 during read and programming operations.

The memory device 101 may comprise a non-volatile memory device and thememory cells 100 can include non-volatile memory cells such that thememory cells 100 can retain information stored therein when power (e.g.,V_(cc), V_(ss), or both) is disconnected from the memory device 101.

Each of the memory cells 100 can include a memory element havingmaterial, at least a portion of which can be programmed to a desireddata state (e.g., by being programmed to a corresponding resistancestate). Different data states can thus represent different values ofinformation programmed into each of the memory cells 100.

The memory device 101 can perform a programming operation when itreceives (e.g., from an external processor or a memory controller) aprogramming command and a value of information to be programmed into oneor more selected ones of the memory cells 100. Based on the value of theinformation, the memory device 101 can program the selected memory cellsto appropriate data states to represent the values of the information tobe stored therein.

One of ordinary skill in the art may recognize that the memory device101 may include other components, at least some of which are discussedherein. However, several of these components are not shown in thefigure, so as not to obscure details of the various embodimentsdescribed. The memory device 101 may include devices and memory cells,and operate using memory operations (e.g., programming and eraseoperations) similar to or identical to those described below withreference to various other figures and embodiments discussed herein.

With reference now to FIG. 2, a partial block diagram of an apparatus inthe form of a memory device 201 is shown to include a memory array 202,including memory cells 200 with access components 211 and memoryelements 222, according to an example embodiment. The memory array 202may be similar or identical to the memory array 102 of FIG. 1. Asfurther shown in FIG. 2, the memory cells 200 are shown to be arrangedin a number of rows 230, 231, 232, along with access lines, for exampleword lines, to conduct signals such as signals WL0, WL1, and WL2. Thememory cells are also shown to be arranged in a number of columns 240,241, 242 along with data lines, for example bit lines, to conductsignals such as signals BL0, BL1, and BL2. The access components 211 canturn on (e.g., by using appropriate values of signals WL0, WL1, and WL2)to allow access to the memory elements 222, such as to operate thememory elements as pass elements, or to read information from or program(e.g., write) information into the memory elements 222.

Programming information into the memory elements 222 can include causingthe memory elements 222 to have specific resistance states. Thus,reading information from a memory cell 200 can include, for example,determining a resistance state of the memory element 222 in response toa specific voltage being applied to its access component 211. In eithercase, such a determining act may involve sensing a current (or absenceof current) flowing through the memory cell 200 (e.g., by sensing acurrent of a bit line electrically coupled to the memory cell). Based ona measured value of the current (including, in some examples, whether acurrent is detected at all), a corresponding value of the informationstored in the memory can be determined. The value of information storedin a memory cell 200 can be determined in still other ways, such as bysensing a voltage of a bit line electrically coupled to the memory cell.

FIG. 3 shows a schematic diagram of a memory cell 300 having an accesscomponent 311 coupled to a memory element 333, according to variousembodiments. Lines labeled WL and BL in FIG. 3 may correspond to any oneof the access lines 104 and any one of the first data lines 106 of FIG.1, respectively. FIG. 3 shows an example of the access component 311including, for example, a metal-oxide-semiconductor field-effecttransistor (MOSFET). As will be realized by a person of ordinary skillin the art, upon reading this disclosure, the memory cell 300 caninclude other types of access components, such as diodes, for example,or may not include any access component, such as in the case of somecross-point arrays.

The memory element 333 may be coupled to and disposed between twoelectrodes, such as a first electrode 351 and a second electrode 352.FIG. 3 schematically shows these electrodes as dots. Structurally, eachof these electrodes can include conductive material. The memory element333 can include material that can be changed, for example, in responseto a signal, to have a different resistance state. The value ofinformation stored in the memory element can correspond to theresistance state of the memory element. The access component 311 canenable signals (e.g., embodied as a voltage or current) to betransferred to and from the memory element 333 via the pairs ofelectrodes during operation of the memory cell, such as during read,program, or erase operations.

A programming operation may use signal WL to turn on the accesscomponent 311 and then apply a signal BL (e.g., a signal having aprogramming voltage or current) through the memory element 333. Such asignal can cause at least a portion of the material of the memoryelement 333 to change. The change can be reversed by, for instance,performing an erase operation. For example, a localized conductiveregion may be formed within an electrolyte contained within the memoryelement 333. The formation of the localized conductive region isdiscussed in more detail, below, for example, with reference to FIGS. 5Athrough 5C. The lateral size of the localized conductive region candetermine the resistance state of the memory cell, where differentresistance states correspond to different data states that representdifferent values of information stored in the memory element 333. Thephysical characteristics of the localized conductive region, and hencethe memory characteristics of the cell, depend on the attributes of thesignal pulse that is used to “set” the cell. For example, a lower energypulse may form a “weaker” (e.g., thinner and/or shorter) conductiveregion that is lower in conductance, and retains the associatedresistance state for only a short duration. In this case, the lowerenergy pulse provides a low-power, short-term memory function. Incomparison, a higher energy pulse may form a “stronger” (e.g., thickerand/or taller) localized conductive region that is higher inconductance, and exhibits longer-term memory retention. In yet anotherexample, a very fast, high power pulse may provide a conductive regionthat is only retained temporarily. In this case, the memory function maybe considered volatile and function in a manner analogous to DRAM. Anyof the prescribed memory functions be utilized in conjunction with othermemory cells (e.g., regions of memory cells), that furnishdifferentiated memory functions, based on their program signalattributes.

A read operation may use the signal WL to turn on the access component311 (or otherwise access the memory cell) and then apply a signal BLhaving a voltage or a current (e.g., a read voltage or current) throughthe memory element 333. The read operation may measure the resistance ofthe memory cell 300, based on a read voltage or current, to determinethe corresponding value of information stored therein. For example, inthe memory cell 300, a different resistance state can impart a differentvalue (e.g., voltage or current value) to signal BL when a read currentpasses through the memory elements 333. Other circuitry of the memorydevice (e.g., a circuit such as the I/O circuit 116 of FIG. 1) can usethe signal BL to measure the resistance state of memory element 333 todetermine the value of the information stored therein.

The voltage or current used during a read, program, or erase operationcan be different from one another. For example, in a programmingoperation, the value (e.g., the voltage) of the signal (e.g., the signalBL in FIG. 3) that creates a current flowing through the memory elementcan be sufficient to cause the material or at least a portion of thememory element to change. The change can alter the resistance state ofthe memory element to reflect the value of the information to be storedin the memory element 333.

In a read operation, the value (e.g., the voltage) of the signal (e.g.,the signal BL in FIG. 3) that creates a current flowing through thememory element can be sufficient to create the current but insufficientto cause any portion of the memory element to change. Consequently, thevalue of the information stored in the memory element can remainunchanged during and after the read operation. Other embodiments mayrequire “refresh” operations, for example volatile memory function suchas DRAM.

In an erase operation, the voltage value of the signal (e.g., the signalBL in FIG. 3) can have an opposite polarity from the voltage used in aprogramming operation. The signal, creating a current in this case, cantherefore change, or reset, the material of the memory element to itsoriginal state; for example, a state prior to any programming beingperformed on the memory cell.

Various ones or all of the memory cells 100, 200, 300 of FIGS. 1 through3 can include a memory cell having a structure similar or identical toone or more of the memory cells described below.

For example, FIG. 4 shows is a simplified schematic block diagram of oneof several memory cells that may be used with the memory devices ofFIGS. 1 and 2, and may be similar to or identical to the memory element333 of FIG. 3. That is, the memory cell 300 may comprise a resistancechange memory cell (RCM) 400. The RCM 400 includes the type of cellknown as a conductive-bridging RAM (CBRAM) memory cell. As described infurther detail below, an operation of the RCM 400 is based on avoltage-driven ionic migration and electrochemical deposition of metalions within a solid electrolyte 409 of the RCM 400.

Prior to any signal (e.g., a bias voltage) being applied to the anode405 and the cathode 407, the basic construction of the RCM 400 is thatof a metal-insulator-metal structure. Therefore, prior to any voltagebeing applied to the anode 405, the RCM 400 can be considered to be in a“reset” (e.g., native) state. The reset state is a high-resistance statedue to the natural insulative (i.e., electrically non-conductive) natureof the solid electrolyte 409. As discussed in more detail with referenceto FIGS. 5A through 5C, below, by applying, for example, a positivevoltage to an anode 405 of the RCM 400, metal ions are driven from theanode 405, through the solid electrolyte 409, and towards a cathode 407.

The anode 405 may be, for example, an oxidizable, fast diffusingmetallic or metallic alloy layer. The anode 405 may be comprised ofvarious types of electrochemically active metals or metal alloys. In aspecific example, the anode 405 may comprise silver (Ag), copper (Cu),Aluminum (Al), or zinc (Zn) and functions as a metallic ion donor. Thecathode 407 may be a relatively inert material comprising asemiconducting or metallic material that does not possess a significantsolubility or a significant mobility to provide ions to the solidelectrolyte 409. In a specific example, the cathode 407 may compriseplatinum (Pt), tungsten (W), titanium (Ti), tantalum (Ta), titaniumnitride (TiN), or doped silicon (Si), tantalum nitride (TaN). Theelectrolyte may be a chalcogenide, for example, silver-doped germaniumselenide (Ag—GeSe), silver-doped germanium sulfide (Ag—GeS₂),copper-doped germanium sulfide (Cu—GeS₂), or copper telluride(CuTe_(x)); or an oxide, e.g. a transition metal oxide (e.g., ZrO_(x)),a semiconductor oxide (e.g., SiO_(x)), a rare earth oxide (e.g.,YbO_(x)), an other metal oxide (e.g., AlO_(x)), or combinations thereof,(e.g., ZrSiO_(x)).

One advantage of the RCM 400 compared with more traditional memorytechnologies (e.g., flash memory) is that the RCM 400 offers potentialfor scaling to smaller technology nodes, and may be operated atcomparatively low power for all operations (e.g., read, program, anderase). Also, these operations may be performed at a higher speed thantraditional memory. For example, to increase the speed of operations,the RCM 400 may be programmed at a relatively low voltage, emulating avolatile memory type (e.g., random access memory (RAM)). The emulationof RAM requires less power but also has a limited data retention life.The data retention life may be increased by applying a higher voltageand/or higher current compliance) signal for a longer time period. Theemulation of various memory types, along with programming/erase (P/E)voltages, and application of voltage pulse times and compliancecurrents, are discussed in more detail, below.

With reference to FIGS. 5A through 5C, a schematic representation ofionic migration and localized conductive region formation and growth isshown. In FIG. 5A, a minimum reaction activation energy 501 (e.g., thereaction energy necessary to overcome an inherent energy barrier) may besupplied by a positive voltage applied to the anode 405. The positivevoltage produces and drives metallic ions 503 from the anode 405,through the solid electrolyte 409, and toward the cathode 407. Themetallic ions 503 deposit on the cathode 407 and may beelectrochemically reduced to form a highly-conductive metal-richdeposit. The electrodeposit may continue to grow as the metallic ions503 continue to migrate from the anode 405 toward the cathode 407, aslong as the positive voltage is applied to the anode 405. A smalllocalized conductive region 505 deposited on the cathode 407 alters atleast one of the electrical resistance and the electron tunnelingcurrent across the junction. The small localized conductive region 505,in conjunction with the metallic ions 503 in the solid electrolyte 409,increases the current sensed across the RCM of FIG. 5A as compared withthe RCM 400 of FIG. 4, which is considered to be in a reset state sinceno voltage has yet been applied.

In FIG. 5B, as the positive voltage is maintained on the anode 405, themetallic ions 503 continue to deposit and the localized conductiveregion continues to grow. The localized conductive region grows awayfrom the cathode 407 and begins approaching the anode 405, forming anenlarged localized conductive region 507. Either the small localizedconductive region 505 of FIG. 5A or the enlarged localized conductiveregion 507 of FIG. 5B may not be a continuous metallic structure but mayinstead be a chain of metal-rich islands. A higher-amplitude programmingsignal or a longer duration of the programming pulse may produce alarger localized conductive region 509 as indicated by FIG. 5C.

With reference to FIG. 5C, with a continuing application of positivevoltage to the anode 405, a larger localized conductive region 509 isformed, eventually bridging the distance, H, 513, between the cathode407 and the anode 405. By continual application of the voltage signal,the larger localized conductive region 509 also continues to growradially as indicated by an approximation of the full-width andhalf-maximum (FWHM) diameter, D_(r), 511 of the larger localizedconductive region 509. Since the larger localized conductive region 509bridges the distance, H, 513 from the cathode 407 to the anode 405, theRCM of FIG. 5C has a lower-resistance state (i.e., a higher-conductivityvalue) than the RCM of FIG. 5B having the enlarged localized conductiveregion 507. In turn, the enlarged localized conductive region 507produces a RCM with a lower-resistance state than the RCM of FIG. 5Athat has the small localized conductive region 505. The RCM of FIG. 5A,in turn, has a lower-resistance state than the RCM 400 of FIG. 4, whichis in a reset state.

To erase the RCM 400, a positive bias signal (positive with respect tothe anode 405) may be applied to the cathode 407. The electrochemicalprocess is reversed, and the electro deposit is oxidized. Metallic ions503 then migrate away from the cathode 407, through the solidelectrolyte 409, back toward the anode 405. The migration of themetallic ions 503 breaks down the localized conductive region and theresistance of the RCM 400 increases. Breaking down the localizedconductive region returns the RCM 400 to a reset state. Thus, the storeddata content of the RCM 400 may be defined by the respective resistancebetween the anode 405 and the cathode 407. Thus, the reverse polaritysignal (i.e., the positive bias on the cathode) can also be used tooperate the device to different states of resistance.

In addition to an ability to emulate various memory function types(e.g., volatile, non-volatile, high-speed, low-power, high-endurance,etc.), the RCM 400 of FIG. 4 offers a resistive switching effect overseveral orders of magnitude. Thus, multi-level memory programming ispossible by programming the RCM 400 to different resistance states. Forexample, a first data state can be achieved by programming (or erasing)the RCM 400 to a high-resistance (low-conductivity) state (e.g., a “1”or reset state). A second data state can be achieved by programming theRCM 400 to a low-resistance (high-conductivity) state (e.g., a “0” orset state). A difference in the resistance states may be based on avariation of the concentration of the metallic atoms either bridging theanode 405 and the cathode 407 with a localized conductive region, or thelocalized conductive region being reduced in size or absent within thesolid electrolyte 409. To read the value of data stored within the RCM400, the access component 311 of the memory cell 300 (see FIG. 3) isswitched on and a small signal, for example a voltage signal, is appliedacross the RCM 400. If a localized conductive region has been formed, aresistance measured across the cell becomes relatively small. If nolocalized conductive region is formed, the resistance will be higher.Consequently, the RCM can be considered to be a variable resistancedevice where each resistance state (e.g., a range of resistance values)corresponds to a different data state.

The incremental growth of the localized conductive region, and resultingdecrease in resistance, can be controlled by at least two factors. Withreference to Table I, below, increasing the applied voltage may increasethe growth (both initially in height, H, and radial growth, D_(r)) ofthe localized conductive region, as well as increase speed. Further,applying a voltage across the anode 405 and the cathode 407 for a longertime period may also increase the growth of the localized conductiveregion. Further, the voltage can be applied in separate pulses. Forexample, rather than applying a single 100 nA pulse at 5.0 V, several-20nA pulses at 5.0 V may be applied subsequently and may produce a similareffect on the localized conductive region growth. The current complianceis provided as an example of an external current limit for variousresistance states during reading, programming, and erasing. For example,if the current through the RCM 400 is too great, Joule-heating effectsmay destroy the localized conductive region.

TABLE I Example operating ranges for differentiated memory functions.Actual operating ranges depend on device specifics, such as materialcomposition, film thicknesses, and fabrication process conditions.Current Memory P/E Voltage P/E Pulse Compliance Retention Function Type(V) Duration (Set/Reset) LRS/HRS (sec) Volatile 0.5-3.0  1 ns-20 ns 10nA-1 μA  1 MΩ/1 GΩ 1e0-1e2 Memory Storage 1.0-5.0 100 ns-10 μs  100nA-100 μA 1 MΩ/1 GΩ 1e4-1e7 Class Memory Storage 1.0-5.0  1 μs-100 μs 10 μA-100 μA 100 kΩ/1 GΩ   1e7-1e8 Memory OTP 3.0-5.0 100 μs-100ms >100 μA ~1 kΩ/NA  >1e8 Memory

While different applications of voltage and time can be selected toproduce different resistance states of the RCM 400 of FIG. 4, thedifferent voltages and times may be used to emulate different types ofmemory as well. For example, shorter pulses at a lower voltage appliedto the RCM 400 can be used to emulate volatile memory (e.g., randomaccess memory). The shorter pulse and lower voltage and current lowersoverall power usage. However, the retention time period for the datastored will be short. If longer data retention is needed, a periodicvoltage pulse refresh may be required to preserve the stored data beyondapproximately a few seconds. Applying either a higher voltage or thesame voltage for a longer duration, or both, can be used to emulatestorage class memories (e.g., phase change memory (PCM) and magnetic RAM(MRAM)) or storage memory (e.g., disk drives). The storage class memorystored in this way can be preserved for weeks or months without arefresh voltage pulse. In some embodiments, the storage memory may bepreserved for several years without a refresh pulse. By applying eitheran even higher voltage to the RCM, or applying the voltage pulse for alonger duration, or both, the RCM can emulate a one-time programmable(OTP) memory (e.g., read-only memory) type. In some embodiments, theOTP-emulated memory may be stored for 20 years or more without aperiodic refresh pulse. For each of the memory function types, exampleresistances are provided for a range of a low resistance state (LRS) toa high resistance state (HRS). In various embodiments, a minimum of aten-times ratio between HRS & LRS may be chosen. The example resistancesmay be used during a read operation of the RCM to determine a datastate.

Each of the voltages, pulse durations, and current compliance settingscan vary with device geometry. Different geometries and design rules mayinvolve the use of higher or lower voltages and currents, and longer orshorter pulse durations, at higher or lower current compliances, whichmay result in longer or shorter retention periods. For example, forminga RCM having a solid electrolyte with a taller height, H (see FIG. 5C),may utilize a higher voltage and/or longer pulse duration to program theRCM for a given memory function. However, the retention period may alsobe longer without a refresh. Similarly, forming a RCM having a solidelectrolyte with a shorter height, H (see FIG. 5C), may utilize a lowervoltage and/or shorter pulse duration to program the RCM for a givenmemory function. However, the retention period may also be shorter,calling for the use of more frequent periodic refresh pulses.

Further, although only four memory function types are shown in Table I,a person of ordinary skill in the art, upon reading and understandingthe disclosure provided herein, will understand that many other memoryfunction types (where the term “memory function types” encompassessub-function types) may be possible. The emulation of additional memoryfunction types is possible due to the trade-offs between programmingpower, retention, and cycling endurance.

Thus, the programming speed can be accelerated by increasing the voltageor decreasing the pulse width of the voltage pulse applied across theRCM 400. The amount of power consumed to program a RCM may be varieddepending upon a given retention period needed for a particular set orsets of data. This can be due to the apparent voltage-time equivalencewithin this class of memory devices: regions of memory cells allocatedfor “faster” operation may require higher voltage operation and morefrequent refresh due to shorter retention. Other regions of memory cellsallocated for “longer-term” memory operations may require longer pulsewidths, for a given voltage, and thus may operate at “slower” speeds.

With reference now to the example of a voltage-time graph 600 of FIG. 6,a number of pulses are shown. The pulses are shown as an absolute valueof voltage as a function of time. Since the same amplitude and durationof pulse may be employed for either programming or erase operations inaccordance with Table I, the amplitude of voltage is shown as anabsolute value. For example, if a positive voltage is applied to theanode 405 of FIG. 4 (positive relative to the cathode 407), then alocalized conductive region within the RCM 400 is either formed or grownand the resistance of the RCM 400 decreases. Thus, the RCM 400 is in aprogram mode of operation. If a negative voltage is applied to the anode405, then the localized conductive region begins to break down, therebyincreasing the resistance of the RCM 400. The RCM 400 is therefore in anerase mode of operation.

A person of ordinary skill in the art, upon reading the disclosureprovided herein, will recognize that the nomenclature for program anderase modes of operation is somewhat arbitrary and may be reversed. Forexample, a data value of “0” can either be considered as being either ahigh-resistance state or a low-resistance state of the RCM 400.Similarly, a data value of “l” can either be considered as being eithera low-resistance state or a high-resistance state of the RCM 400, aslong as it is the opposite resistance state of the data “1” value.

Therefore, a data state for any of the states may be programmed orerased by a number of signal pulses. For the continuing discussions,below, reference will be made only to the programming pulses. A personof ordinary skill in the art will understand, based on the discussionprovided herein, that a similar understanding of the description appliesto an erase operation as well.

For example, with concurrent reference to Table I and continuingreference to FIG. 6, a first pulse 601 has a relatively low-amplitudewith a relatively short duration. The first pulse 601 may be sufficientto begin formation of a small localized conductive region 505 within theRCM 400 (e.g., see FIG. 5A). The small localized conductive region 505lowers the resistance of the RCM 400 from a reset state and may allowthe RCM 400 to emulate a volatile memory function type due to thelow-amplitude and short-duration of the pulse.

A second pulse 603 has approximately the same amplitude as the firstpulse 601 but has a longer duration. Therefore, the second pulse 603 maybe sufficient to provide a higher conductance (e.g., an enlargedportion) of the enlarged localized conductive region 507 within the RCM400 (e.g., see FIG. 5B). The enlarged localized conductive region 507lowers the resistance of the RCM 400 even farther from the reset stateand may allow the RCM 400 to emulate a storage class memory functiontype, and therefore an increased retention, due to the low-amplitude andlonger-duration of the second pulse 603.

A third pulse 605 has a larger amplitude than either the first pulse 601or the second pulse 603, but has a duration approximately the same asthe first pulse 601. However, the increased amplitude of the third pulse605 may still be sufficient to provide a higher conductance (e.g., alarger portion) of the larger localized conductive region 509 within theRCM 400 (e.g., see FIG. 5C). Like second pulse 603, the larger localizedconductive region 509 lowers the resistance of the RCM 400 even fartherfrom the reset state and may allow the RCM 400 to emulate a storagememory function type due to the high-amplitude and shorter-duration ofthe third pulse 605. Alternatively, the increased amplitude may providefaster program and erase operations and may allow the RCM 400 to emulatea high-speed, volatile memory function analogous to DRAM.

As an alternative to the third pulse 605, a pair of pulses 607 may besufficient to place the RCM 400 in the same state as the third pulse605. Even though the amplitude of the pair of pulses 607 is less thanthat of the third pulse 605, the integration of voltage and time (i.e.,Joules/Amp) may be approximately the same as is contained within thethird pulse 605. Therefore, the pair of pulses 607 may still besufficient to provide a higher conductance (e.g., an enlarged portion)of the larger localized conductive region 509 within the RCM 400.

Referring now to FIG. 7, an embodiment of an apparatus in the form of amemory circuit 700 is shown to implement the variable resistance statesand memory function types described herein. The memory circuit 700 canbe formed on a single die 710 and is shown to include control and selectcircuitry 701, drive circuitry 703 (e.g., a plurality of drive circuits703A, 703B, 703C, 703D), and a plurality of memory regions (e.g., memoryarrays 705A, 705B, 705C, 705D). The control and select circuitry 701 maycontrol memory operations based on signals of incoming control lines(e.g., the control lines 120 of FIG. 1). Examples of the signals on thecontrol lines can include one or more clock signals and other signals toindicate which operation (e.g., a programming or read operation) isperformed on a respective one or ones of the memory regions. Otherdevices external to the memory circuit 700 (e.g., a processor or aseparate memory controller) can control the values of the controlsignals on the control lines. Specific combinations of values of thesignals on the control lines can produce a command (e.g., a programmingor read command) that can cause the memory circuit 700 to perform acorresponding memory operation (e.g., a program or read operation). Thecontrol and select circuitry 701 may interpret flag bits that anexternal controller might set to indicate what type of memory functionis indicated for given data. The control and select circuitry 701 mayalso include column and row decoder circuitry.

Each of the plurality of memory arrays 705A, 705B, 705C, 705D may beused to emulate a specific (and perhaps different) memory function type.For example, the memory array 0 705A may comprise a group of RCMs toemulate a volatile memory function, the memory array 1 705B may comprisea group of RCMs to emulate a storage class memory function, the memoryarray 2 705C may comprise a group of RCMs to emulate a storage memoryfunction, and the memory array 3 705D may comprise a group of RCMs toemulate a one-time programmable (OTP) memory function.

Commensurate with the function to be emulated, the plurality of memoryarrays, the plurality of drive circuits may be configured to match thepower requirements of a related memory array. For example, if the memoryarray 0 705A contains an array of RCMs to emulate volatile memory, thenthe drive elements within the drive circuit 0 703A may be sized smallerthan drive circuits on other arrays since the power output requirements(e.g., the maximum voltages and current compliance levels) for volatilememory emulation are smaller than for other types of emulated memoryfunction types. In other cases, the drive elements within the drivecircuit 0 703A may be sized similarly or even larger than drive circuitson other arrays since the fast-operating volatile memory may utilize ashort, high-voltage pulse in order to provide sufficient drift velocityto set the cell in the short time allotment.

Although there is no need to arrange the memory arrays into differentphysical locations, each emulating a specific memory function type, adesigner of the circuit may find the physical layout of FIG. 7 to beadvantageous for layout and design purposes. Further, the plurality ofdrive circuits 703A, 703B, 703C, 703D may be replicated by a singledrive circuit where each drive element (e.g., a drive transistor) withinthe single drive circuit is capable of applying the entire range ofvoltage pulses (see Table I) within the current compliance level.However, by arranging the drive circuits to match a given memory arrayemulating a given memory function type, the physical size of the memorycircuit 700 may be reduced. Consequently, the overall area for thememory circuit 700 may be reduced if all drive elements are not designedto cover a full power range.

Further, although the memory circuit 700 is shown to be formed as asingle integrated circuit device (e.g., the single die 710), a person ofordinary skill in the art, upon reading and understanding the disclosureprovide herein, will realize that various components of the memorycircuit 700 may be arranged on separate integrated circuit devices. Forexample, each of the plurality of drive circuits may be physicallylocated on an integrated circuit separate from the plurality of memoryarrays.

Thus, different regions of the single die 710 may be operated fordifferentiated memory function types, based on applying differentprescribed program signals (e.g., different pulse amplitudes and/orpulse widths), as described herein in order to obtain differentretention and power characteristics. Therefore, each region of thesingle die 710 may have corresponding transistor access devices in thedrive circuitry 703 that are specifically designed to provide thedifferent drive currents necessary for the differentiated memoryfunction types. All transistor access devices may be fabricated in thesame layer or layers within the device, and all memory cells may bewithin the same layer or layers of the device.

Referring now to FIG. 8, a flowchart shows an embodiment of a method 800to implement variable resistance states and memory function types of aRCM. At operation 801, a determination is made as to what type of memoryfunction is to be emulated. For example, if the data are to be storedfor a very short time period, such as to emulate a cache memory, thenhigh programming speeds may be more important than data retention times.Conversely, if archival data storage is needed, programming times may befar less important than retention times.

Once the determination is made as to what type of memory function toemulate, then memory locations are determined at operation 803. Based onthe earlier determination of memory emulation type at operation 801, adetermination of voltage pulse amplitude and duration is made atoperation 805. The determination of pulse voltage and duration may bedetermined with the aid of Table I. If a determination is made atoperation 805 that the voltage exceeds, for example, an available powersupply voltage, then operation 807 may be performed when a ramp-up involtage (i.e., a voltage ramp) is required. For example, if a maximumvoltage on a power rail is only 1.8 V but the programming voltagerequirement is 3.0 V or more, then a separate voltage-assist mechanism,such as a charge pump, may be activated at operation 811 to deliver thedesired programming voltage. Voltage assist mechanisms, such as chargepumps, are known independently by those of ordinary skill in the art.

At operation 813, a specific RCM is accessed by selecting the accesscomponent to operate. The access component may be similar or identicalto the access component 313 of FIG. 3. The determined amplitude of thevoltage pulse is then applied to the RCM for the determined timeduration at operation 815 and the data are stored in the RCM atoperation 817. A person of ordinary skill in the art, upon reading andunderstanding the disclosure provided herein, will recognize thatseveral of the acts detailed with respect to the method 800 areoptional, and, also, may be performed either in parallel or in an orderdifferent than that shown.

With reference now to FIG. 9, a block diagram of an illustrativeembodiment of an apparatus in the form of a system 907 (e.g., anelectronic system) including one or more memory devices (e.g., thememory device 101 of FIG. 1 or the memory circuit 700 of FIG. 7) isshown. The system 907 may be used in devices such as, for example, apersonal digital assistant (PDA), a laptop or portable computer with orwithout wireless capability, a web tablet, a wireless telephone, apager, an instant messaging device, a digital music player, a digitalcamera, or other devices that may be adapted to transmit or receiveinformation either wirelessly or over a wired connection. The system 907may be used in any of the following systems: a wireless local areanetwork (WLAN) system, a wireless personal area network (WPAN) system,or a cellular network.

The system 907 of FIG. 9 is shown to include a controller 903, aninput/output (I/O) device 915 (e.g., a keypad, a touchscreen, or adisplay), a memory device 913, a wireless interface 911, and a staticrandom access memory (SRAM) device 901 coupled to each other via a bus909. A battery 905 may supply power to the system 907 in one embodiment.The memory device 913 may include a NAND memory, a flash memory, a NORmemory, a combination of these, or the like, as well as one or more ofthe novel memory devices described herein.

The controller 903 may include, for example, one or moremicroprocessors, digital signal processors, micro-controllers, or thelike. The memory device 913 may be used to store information transmittedto or by the system 907. The memory device 913 may optionally also beused to store information in the form of instructions that are executedby the controller 903 during operation of the system 907 and may be usedto store information in the form of user data either generated,collected, or received by the system 907 (such as image data). Theinstructions may be stored as digital information and the user data, asdisclosed herein, may be stored in one section of the memory as digitalinformation and in another section as analog information. As anotherexample, a given section at one time may be labeled to store digitalinformation and then later may be reallocated and reconfigured to storeanalog information. The controller 903 may include one or more of thenovel memory devices described herein.

The I/O device 915 may be used to generate information. The system 907may use the wireless interface 911 to transmit and receive informationto and from a wireless communication network with a radio frequency (RF)signal. Examples of the wireless interface 911 may include an antenna,or a wireless transceiver, such as a dipole or patch antenna. However,the scope of the inventive subject matter is not limited in thisrespect. Also, the I/O device 915 may deliver a signal reflecting whatis stored as either a digital output (if digital information wasstored), or as an analog output (if analog information was stored).While an example in a wireless application is provided above,embodiments of the inventive subject matter disclosed herein may also beused in non-wireless applications as well. The I/O device 915 mayinclude one or more of the novel memory devices described herein.

The various illustrations of the methods and apparatuses herein areintended to provide a general understanding of the structure of variousembodiments and are not intended to provide a complete description ofall the elements and features of the apparatuses and methods that mightmake use of the structures, features, and materials described herein.

The apparatuses of the various embodiments may include or be includedin, for example, electronic circuitry used in high-speed computers,communication and signal processing circuitry, single or multi-processormodules, single or multiple embedded processors, multi-core processors,data switches, and application-specific modules including multilayer,multi-chip modules, or the like. Such apparatuses may further beincluded as sub-components within a variety of electronic systems, suchas televisions, cellular telephones, personal computers (e.g., laptopcomputers, desktop computers, handheld computers, tablet computers,etc.), workstations, radios, video players, audio players, vehicles,medical devices (e.g., heart monitors, blood pressure monitors, etc.),set top boxes, and various other electronic systems.

A person of ordinary skill in the art will appreciate that, for this andother methods (e.g., programming or read operations) disclosed herein,the activities forming part of various methods may be implemented in adiffering order, as well as repeated, executed simultaneously, orsubstituted one for another. Further, the outlined acts and operationsare only provided as examples, and some of the acts and operations maybe optional, combined into fewer acts and operations, or expanded intoadditional acts and operations without detracting from the essence ofthe disclosed embodiments.

The present disclosure is therefore not to be limited in terms of theparticular embodiments described in this application, which are intendedas illustrations of various aspects. Many modifications and variationscan be made, as will be apparent to a person of ordinary skill in theart upon reading and understanding the disclosure. Functionallyequivalent methods and apparatuses within the scope of the disclosure,in addition to those enumerated herein, will be apparent to a person ofordinary skill in the art from the foregoing descriptions. Portions andfeatures of some embodiments may be included in, or substituted for,those of others. Many other embodiments will be apparent to those ofordinary skill in the art upon reading and understanding the descriptionprovided herein. Such modifications and variations are intended to fallwithin a scope of the appended claims. The present disclosure is to belimited only by the terms of the appended claims, along with the fullscope of equivalents to which such claims are entitled. It is also to beunderstood that the terminology used herein is for the purpose ofdescribing particular embodiments only and is not intended to belimiting.

The Abstract of the Disclosure is provided to comply with 37 C.F.R.§1.72(b), requiring an abstract allowing the reader to quickly ascertainthe nature of the technical disclosure. The abstract is submitted withthe understanding that it will not be used to interpret or limit theclaims. In addition, in the foregoing Detailed Description, it may beseen that various features are grouped together in a single embodimentfor the purpose of streamlining the disclosure. This method ofdisclosure is not to be interpreted as limiting the claims. Thus, thefollowing claims are hereby incorporated into the Detailed Description,with each claim standing on its own as a separate embodiment.

What is claimed is:
 1. An apparatus, comprising: a number of resistance change memory (RCM) cells; and drive circuitry electrically coupled to each of the number of RCM cells to provide a signal pulse, the signal pulse having a selectable attribute configured to emulate a determined memory function type, to one or more selected ones of the number of RCM cells. 